The present invention relates to a voltage detection system and a controlling method of the same.
FIG. 10 shows a block diagram of a voltage detection circuit described in Group hardware manual pp. 799-821 for RENESAS 16-bit single-chip microcomputer H8S family/H8STiny series H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, and H8S/20235 as a related art. The voltage detection circuit detects a decrease in power supply voltage to prevent malfunction (erratic operation) of an LSI system mounted with the voltage detection circuit. The voltage detection circuit can save data to be restored to a state before the voltage drop after the power supply is recovered to the normal voltage.
As shown in FIG. 10, the voltage detection circuit includes a ladder resistor, a detection voltage generation circuit, a comparator, a reset control circuit, an interrupt control circuit, a register capable of being rewritten by a CPU instruction, and a control circuit that changes processes based on register values. For example, a comparator LVD1 compares a voltage divided by the ladder resistor with Vdet1 generated from the detection voltage generation circuit.
The control circuit is supplied with a detection signal from the comparator LVD1 to detect the state of the power supply voltage. The detection signal is used to determine whether the current power supply voltage conforms to an operating voltage. Accordingly, transition to the standby mode is possible at the operating voltage or higher during normal operation. The system stability can be improved by the elimination of an instable state where the power supply voltage becomes lower than the operating voltage.
FIG. 11 is a flowchart showing operations of the voltage detection circuit. As shown in FIG. 11, the system starts and then the CPU sets the register to configure an operation mode and a first detection level (step S1). A timer operates on software processing for the wait time long enough to stabilize the detection level (step S2). The CPU then sets the register to enable low-voltage detection (step S3). For example, this signifies that the control circuit becomes ready for accepting a detection signal from the comparator LVD1. Steps S1 through S3 or an equivalent operation is referred to as a CPU process.
The process is then passed to the hardware. For example, the comparator LVD1 monitors a decrease in the power supply voltage. The comparator LVD1 detects that the power supply voltage decreases and becomes equal to the first detection level (Yes at step S4). Control is passed to the CPU process at steps S5 through S7 equivalent to steps S1 through S3 as mentioned above in order to change the operation mode and the detection mode. Specifically, the CPU sets the register to configure an operation mode and a second detection level (step S5). The timer operates on software processing for the wait time long enough to stabilize the detection level (step S6). The CPU then sets the register to enable low-voltage detection (step S7).
Upon completion of the CPU process at step S7, control is passed to the hardware. For example, a comparator LVD2 monitors a decrease in the power supply voltage. The detection level is changed to the operating voltage (second detection level). The comparator LVD2 compares the second detection level with the power supply voltage (step S14). When the power supply voltage becomes lower than the second detection level, the comparator LVD2 resets the system (step S15).
At step S4, the comparator LVD1 may detect that the power supply voltage decreases and becomes equal to the first detection level. In this case, the system starts a data saving program (step S8). When the data saving process is complete (Yes at step S9), the main process awaits a request from a CPU instruction to change the operation mode and the detection level (step S10).
When the CPU issues a change request (Yes at step S10), control is passed to the CPU process at steps S11 through S13 equivalent to steps S1 through S3 as mentioned above. Specifically, the CPU sets the register to configure the operation mode and the first detection level (step S11). The timer operates on software processing for the wait time long enough to stabilize the detection level (step S12). The CPU then sets the register to enable low-voltage detection (step S13). The power supply is ready to be restored to the original condition (step S16).